Sensor Open Systems Architecture (SOSA) S3C & HPSC Turn-Key Product Development System

Board Computer PSC = Power Supply Card Purpose NASA is seeking to spur the development of an industry wide ecosystem of standardized interoperable cards that can be used to implement complete spacecraft avionics systems based on the SOSA� S3C profiles. To guarantee interoperability the SOSA� Space Subcommittee, comprising members from NASA, USSF and industry, have been working on a spacecraft avionics standard derived from the VITA 78 (Space VPX) specification. Initial elements of the standard are documented in the recently released SOSA Standard Snapshot 3(see SOSA Space Appendix), which has garnered broad industry support. The purpose of this RFI is to gather information which could eventually lead to a JPL RFP soliciting the development of one or more S3C SpaceVPX compliant development kit(s) for both commercial industry and government organizations. To this end, information is requested related to integrated development kits, as well as constituent products that can be included in a development kit (i.e. PICs, PSCs, software). NASA is proposing SBCs in this development kit be based on the High-Performance Spaceflight Computing (HPSC) processor, currently in development with Microchip Technology Inc. in a partnership with NASA and JPL, using the SOSATM S3C SBC Slot Profile. Overview The development kit is part of a broader NASA effort to advance space-based computing through the Sensor Open System Architecture (SOSA�) and its Space Subcommittee (S3C). The SOSA� S3C aims to create a standardized and interoperable framework for space systems, encouraging collaboration among government agencies, industry, and academia to develop interoperable hardware and software solutions. This effort will support the creation of turn-key systems for testing, development, and flight, enabling more efficient and cost-effective space mission planning and execution. Background NASA�s High Performance Spaceflight Computing (HPSC) project is delivering purpose-built space computing technology for high performance computing. The High-Performance Spaceflight Computing (HPSC) project, a collaboration between NASA and Microchip Technology Inc., is finalizing a cutting-edge, radiation-hardened flight processor that offers 100 times the computational power of current spaceflight computers. It will provide high performance AI dataflow processing with scalable vector computing capabilities that are critical for the science and autonomy needs of future advanced space systems. HPSC is Fault-Tolerant: specially designed to survive in space and contains features that ensure it can operate correctly and provide reliable results in the harshest of natural space environments. This ensures the most critical operations such as: Robotically landing on or flying on another planet Supporting astronauts far from the earth Operating near small bodies in the outer solar system HPSC builds on Industry-Standards. The core of the HPSC design is an industry standard RISC-V based CPU bundled with significant fault and radiation tolerance, and a full security suite as well as all the software required to run it. The HPSC also includes a suite of features and industry-standard interfaces and protocols not previously available for space applications. HPSC offers a variety of advanced capabilities: Space-grade 64-bit Processor Architecture: Includes eight SiFive RISC-V X280 64-bit CPU cores supporting virtualization and real-time operation, with vector extensions that deliver up to 2 TOPS (int8) or 1 TFLOPS (bfloat16) of vector performance for implementing AI/ML processing for autonomous missions. High-speed network connectivity: Includes a 240 Gbps Time-Sensitive Networking (TSN) Ethernet switch for 10GbE connectivity. Also supports scalable and extensible PCIe� gen 3 and Compute Express Link� (CXL�) 2.0 with x4 or x8 configurations and includes RMAP-compatible SpaceWire ports with internal routers. Low-latency data transfers: Includes Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCEv2) hardware accelerators to facilitate low-latency data transfers from remote sensors without burdening compute performance � maximizing compute capabilities by bringing data close to the CPU. Platform-level defense grade security: Implements defense-in-depth security with support for post-quantum cryptography and anti-tamper features. High fault-tolerance capabilities: Supports Dual-Core Lockstep (DCLS) operation, WorldGuard hardware architecture for end-to-end partitioning and isolation, and an onboard System Controller for fault monitoring and mitigation. Flexible power tuning: Includes dynamic controls to balance the computational demands required by the multiple phases of space missions with tailored activation of functions and interfaces. For more information on the HPSC capabilities please contact Microchip Technology Inc. (tao.lang@microchip.com) SOSA� S3C/HPSC Development system Overview The SOSA� S3C/HPSC development system comprises a lab-grade hardware suite and accompanying software that, together, offer a versatile platform for developing and testing hardware and software for space applications. These systems should have a viable path to and should be form, fit, and function equivalent to an eventual flight model. Below are some examples use cases that highlight the potential applications and benefits of the development system: Development of Flight Software: Use Case: Engineers can use the development system to develop and validate flight software such as NASA�s Core Flight Executive/Core Flight Software (CFE/CFS) and the F prime (F�) framework developed by JPL. Benefits: This allows for thorough testing in a controlled environment, ensuring that the software performs reliably under different conditions. Hardware Integration and Testing: Use Case: The development system can be used to integrate various PICs and other infrastructural hardware elements into a multi-slot S3C chassis. This includes components like PSCs, SBC, data storage cards, IO expanders, and more. Benefits: This facilitates comprehensive hardware testing, ensuring compatibility and functionality of different components within the system. Prototype and Engineering Model Development: Use Case: The system can support the development of prototypes and engineering models of flat sats and similar flight systems. These prototypes can be tested for various parameters, including performance, reliability, and resilience to environmental factors. Benefits: Early identification and resolution of potential issues, leading to more robust and reliable flight systems. Educational and Training Purposes: Use Case: Academic institutions and training centers can use the development system to educate students and professionals about space system design and testing. Benefits: Provides hands-on experience with real-world hardware and software used in space missions, enhancing the skills and knowledge of the next generation of aerospace engineers. Collaborative Development and Standardization: Use Case: The system can be used by different organizations (e.g., NASA, JPL, AFRL, Aerospace primes) to collaboratively develop and refine standards for space systems, such as those defined by the SOSA� S3C. Benefits: Promotes interoperability and standardization across different space missions and organizations, leading to more efficient and cost-effective developme